A known converter, for example a flash converter such as the one shown in FIG. 3, includes a plurality of comparators 1, which receive an input signal Vin in addition to a reference signal generated by a string of resistors 2. Depending on the value of the input signal Vin, the comparators can have an output signal which is higher than the input signal, for example, a logic value of 1, or the comparator can have an output signal which is lower than the input signal, a logic value of 0. Therefore, at the output of the comparators, a plurality of bits are obtained in which some have the logic value 1 and others have the logic value 0. Accordingly, the output is a thermometer code, which must be converted into a more suitable code, for example, a Gray code.
The logic circuit 3 shown in FIG. 3 is designed to convert the thermometer code output from the comparators 1 into a code in which, for example, all the bits have the value 0 except for the single bit that indicates the value of the input signal Vin. The logic value 1 output from the logic circuits 3 indicates the transition point, i.e. the point at which the output signal of the comparator changes from the value 1 to the value 0 or vice versa. The object is to output a numeric code which is the equivalent of the input signal Vin. Therefore, the logic circuits 3, which are usually gates of the NOR or NAND type, output a plurality of bits, only one of which is different from all the others.
A PLA type decoder 4 is cascade-connected to the logic circuits 3. It appropriately decodes the signal received from the logic circuits 3 in order to output a signal which indicates the value of the input signal Vin.
FIG. 2 illustrates an example of a known type of PLA which shows, by way of example, only three inputs IN0, IN1, IN2 and three outputs OUT0, OUT1, OUT2. In FIG. 2, the output lines designated by OUT0-OUT2 are connected to the inputs IN0-IN1 through a plurality of transistors of the NPN type. In particular, the transistors 10 and 11 are connected to the input IN2 and their base and collector terminals are common-connected and connected to the output lines OUT2 and OUT1 respectively. The transistors 12 and 13 are instead connected to the input IN1 and their base and collector terminals are common-connected and connected to the output lines OUT2 and OUT0 respectively. Finally, the transistor 14 is connected to the input IN0 and to the output line OUT1.
All the NPN bipolar transistors 10-14 are connected to the supply voltage by their respective collector terminals. Current sources 15, 16 and 17 are provided for the output lines.
The above-proposed structure, shown in FIG. 2, suffers the drawback caused by the output dynamic range of the signal being limited by the need to have high speed logic circuits 3 (as shown in FIG. 3) upstream of the PLA decoder 4. Accordingly, the output signal may not be determined with certainty, because the difference in voltage levels between a logic value 1 and a logic value 0 is very small.